1. Field of the Invention
The present invention relates generally to a multi-processor computer system and, more particularly, to a method and apparatus for distributing housekeeping functions between multiple processors in a multi-processor computer system.
2. Related Art
A computer typically has one or more central processing units (xe2x80x9cprocessorsxe2x80x9d) in addition to dedicated functional units, such as a memory, a bus arbitration unit, a memory refresh controller, and one or more data and instruction caches, all of which will be referred to herein as xe2x80x9ccomponents.xe2x80x9d A computer system having more than one processor will be called a multi-processor system.
Communication between the processors and components takes place over a system bus that interconnects the components and processors. Communication over the bus takes place in a xe2x80x9ctransaction.xe2x80x9d As is well known, instances may arise in which more than one processor is trying to issue a transaction on the bus at the same time. The process of determining which of the processors will control the bus and hence be allowed to issue a transaction on the bus in this situation is referred to as arbitration. The processor that wins the arbitration is referred to herein as the xe2x80x9cbus master.xe2x80x9d
Arbitration takes place in the bus arbitration unit. In a single processor system, the bus arbitration unit may be external to the processor or may be internal to the processor. A functional unit such as a bus arbitration unit will be referred to as xe2x80x9cinternalxe2x80x9d when the functions performed by the functional unit are at least partially performed by the processor. Conversely, a functional unit will be referred to as xe2x80x9cexternalxe2x80x9d when the functions performed by the functional unit are not performed by the processor. As is well known in the art, an external functional unit typically includes dedicated circuitry configured to perform a specific set of functions.
FIG. 1 illustrates an exemplary multi-processor computer system using an external bus arbitrator to perform bus arbitration. As shown in FIG. 1, the multi processor system has a host 10 and a plurality of processors 12a, 12b . . . 12n all connected to a system bus 14. An external arbitration unit 13 receives signals on bus request lines (R) and determines which of the requesting processors should be granted bus mastership according to any known protocol. The processor (or host) that wins the arbitration is notified via a signal on an acknowledge line (A) connecting the arbitrator 13 and the processor or host. To become bus master, a processor asserts a signal on its bus request line (R) and waits for the external bus arbitration unit 13 to grant it mastership of the bus via a signal on its associated acknowledge line (A). Arbitration using an external bus arbitrator thus requires both a request and an acknowledge line for each processor.
In many computer systems, including the system illustrated in FIG. 1, different types of transactions are deemed to be more important than other types of transactions. For example, a computer system may give transactions involving direct memory access (DMA) priority over other types of transactions. To accommodate requests of varying priority, it is common in such systems to interconnect the processors 12a-12n the and bus arbitration unit 13 with one or more priority request lines (P). When a processor desires to issue a priority transaction on the bus, the processor asserts a signal over its priority request line. The external arbitration unit 13 processes the request and assigns the bus preferentially to the processor asserting the signal over the priority request line.
Arbitration using an external bus arbitration unit 13 may become space intensive since multiple dedicated lines must be provided to interconnect each processor 12a-12n and host 10 with the external arbitration unit 13. In the illustrated example, one request line, one acknowledge line, and at least one priority request line are necessary to perform bus arbitration for each processor. When the number of processors connected to the bus is large, a significant amount of space is required to be used for arbitration.
In addition to multiple processors, computers typically employ solid-state memory components such as dynamic random access memory (DRAM) components. The term DRAM will be used herein to refer to any type of dynamic random access memory, including DRAM (dynamic RAM), SDRAM (synchronous DRAM), DRDRAM (direct rambus DRAM), and other types of memory.
Digital information held in DRAM is generally in the form of charge stored on a two dimensional array of capacitors. The charge stored on each capacitor may be sensed during a read operation or changed during a write operation. Additionally, charge is steadily lost over time due to leakage. The amount of leakage depends upon processing and operating conditions, as well as on environmental factors such as temperature and supply voltage. Because of this leakage, the charge on individual capacitors in the capacitor array of the DRAM must be refreshed periodically.
To perform a refresh operation, digital information is conventionally read from the DRAM and immediately re-written into the DRAM. In this way, the charge on the individual capacitors may be enhanced without changing the content of the memory array. To ensure the integrity of the content of the memory array, the DRAM must be refreshed before the leakage causes the charge stored in the capacitors to drop below a predetermined level. Since DRAM is typically organized in rows and columns, refresh of the DRAM is performed typically row-by-row, although other refresh schemes are also possible.
Control of the DRAM refresh procedure in a multiple processor environment is typically handled by an external DRAM refresh controller. The external DRAM refresh controller has a refresh counter indicating the row to be refreshed and a reset enabling the refresh counter to be reset, for example, to the first row. Although the functions performed by the DRAM refresh controller are important to operation of the computer, the DRAM refresh controller consumes valuable space that otherwise could be used for other components. Additionally, the DRAM refresh controller must be connected to the DRAM either through one or more dedicated lines or over the system bus. When the DRAM refresh controller uses the system bus to control DRAM refresh operations, system performance as a whole is degraded by reducing the amount of data that otherwise could be transferred. When the DRAM refresh controller is connected to the DRAM through one or more dedicated lines, valuable space is consumed that could otherwise be used for other purposes.
Accordingly, what is needed is a method and apparatus that will facilitate performance of maintenance functions, such as bus arbitration and DRAM refresh operations, in a multi-processor environment while minimizing the amount of space and other system resources required to perform these functions.
The present invention is a method and apparatus that will facilitate performance of maintenance functions, such as bus arbitration and DRAM refresh operations, while minimizing the amount of space required to perform these functions in a multi-processor environment.
In one embodiment of this invention, each processor is provided with a local arbitration unit of common configuration with the other local arbitration units to perform bus arbitration simultaneously. Each local arbitration unit monitors requests to become bus master by itself and other processors, is synchronized with the other arbitrators, and is provided with similar logic. Accordingly, each local arbitration unit independently determines the identity of the subsequent bus master. By providing local arbitrators that each independently determine allocation of bus mastership, the multi-processor system is able to eliminate the need for acknowledge lines associated with arbitration. This greatly reduces the amount of area required for arbitration.
Similarly, to perform DRAM refresh operations, each processor is provided with a local DRAM refresh controller having at least one pin connected to one or more dedicated DRAM refresh lines. In a preferred embodiment, each processor has one pin connected to a single DRAM refresh line. Each local DRAM refresh controller, when responsible for performing DRAM refresh operations, issues DRAM refresh signals to the DRAM over the DRAM refresh line. When not responsible for performing DRAM refresh operations, each local DRAM refresh controller monitors the DRAM refresh line, senses DRAM refresh signals issued by other DRAM refresh controllers, and uses the sensed signals to update its DRAM refresh row counter. A reset line may also be provided to reset the counter. Alternatively, reset of the controller may be performed via the single DRAM refresh line. Providing each processor with a local DRAM refresh controller eliminates the need for an external DRAM refresh controller thus saving space and removing the DRAM refresh controller as a contending component for mastership of the bus. Also, by ensuring that each DRAM refresh controller has current information relating to DRAM refresh operations, duplication of refresh operations is minimized during hand-offs between processors. Thus, the newly responsible DRAM refresh controller is able to continue the DRAM refresh operation where the last processor""s DRAM refresh controller stopped.